// 1. 时钟分频模块 - 生成10Hz时钟信号（0.1秒周期）
module clk_divider(
    input clk,
    input rst_n,
    output reg clk_100ms
);
    // 输入时钟100MHz，0.1秒需要计数10,000,000
    parameter COUNTER_MAX = 5000000 - 1;
                             
    reg [23:0] counter;
    
    always @(posedge clk or negedge rst_n) 
    begin
        if (!rst_n) begin
            counter <= 0;
            clk_100ms <= 0;
        end else begin
            if (counter >= COUNTER_MAX) 
            begin
                counter <= 0;
                clk_100ms <= ~clk_100ms;
            end 
            else 
            begin
                counter <= counter + 1;
            end
        end
    end
endmodule